1. Field of the Invention
The present invention is directed to non-volatile semiconductor memory devices, and more particularly, to a DRAM cell having a tunnel oxide or dual electron injector structure disposed between a storage node and a floating gate for volatile data retention during power interruptions in a compact one transistor structure.
2. Description of the Prior Art
A dynamic random, access memory (DRAM) cell is very fast and compact but its contents must be refreshed periodically. In addition, a DRAM cell may be referred to as a volatile cell since information stored in the cell is completely lost when the power supply voltage applied to the memory cell is interrupted or turned off. As a result, when there is a power failure, information stored in present day random access memories is lost. Thus, there is a need for volatile dynamic random access memories (DRAM) in the electronic industry.
In contrast with volatile memory cells, the contents of a volatile memory cell, such as an electrically erasable programmable read only memory (EEPROM) cell, are preserved when the power supply is turned off. However, existing EEPROM cells are much slower than DRAM cells and are subject to wear each time information is written into the cell. Thus, EEPROMs cannot be used as the main memory of a computer.
To overcome the limitations of DRAMs and EEPROMs, various volatile RAM cells which merge DRAM and EEPROM cells together have been proposed. For example, in an article entitled "A New Architecture for the NVRAM--An EEPROM Backed-Up Dynamic Ram", by Y. Terada et al., IEEE J. Solid State Circuits, 23(1): p. 86 (1988), a DRAM cell is electrically coupled with an EEPROM cell to provide a non-volatile RAM cell. This cell consists of four n-channel transistors and a capacitor. In this cell, data can be transferred from DRAM to EEPROM in parallel for all cells. A similar non-volatile RAM cell that also allows the simultaneous transfer of the entire DRAM data to EEPROM is disclosed in an article entitled "A Novel NVRAM Cell Technology for High Density Applications" by Y. Yasmauchi et al., IEDM, p. 416 (1988). In this non-volatile RAM cell, a standard DRAM cell is electrically coupled with a conventional FLOTOX EEPROM cell. The cell consists of two transistors, a memory transistor having a floating gate and a storage capacitor. In an article entitled "Dynamic Non-Volatile and Electrically Erasable Read-Only Memories" by H. L. Kalter et al., IBM Technical Disclosure Bulletin, p. 540 (1982), a DRAM cell is made non-volatile by utilizing a four terminal floating gate device and a dual electron injector structure (DEIS) between the floating gate and a first control gate. A similar non-volatile DRAM cell is disclosed in an article entitled "Non-Volatile Dynamic Random Access Memory Cell with Built-In Boosting" by B. A. Kaufman et al., IBM Technical Disclosure Bulletin, p. 1182 (1985). In addition to using a DEIS stack between the floating gate and the control gate, this non-volatile DRAM cell utilizes a DEIS stack between a boost plate and the storage plate of an integrated voltage-boosting capacitor. Although all of the above non-volatile DRAM cells overcome some of the limitations of DRAMs and EEPROMs, they have more complicated cell structures, require larger cell areas and more complicated fabrication processes than existing DRAM cells.
One device dynamic volatile memory cells having the capability of storing data non-volatilely are known. For example, in commonly assigned U.S. Pat. No. 4,471,471, there is disclosed a one device non-volatile DRAM cell which requires a DEIS between a floating gate and a transfer gate. This device uses the floating gate for storing information non-volatilely during power failure and utilizes the DEIS stack over the transfer gate for data recovery after resumption of power. A main disadvantage of this cell is that since the DEIS stack is located on the bit line side of the cell, data cannot be transferred from the DRAM to the floating gate in parallel in all cells. The data first has to be read out by turning on the transfer transistor and reading the voltage on the bit line. Next, depending on the contents, the programming voltage has to be applied on the bit line one cell at a time which is very time consuming. Thus, there is a need to develop a non-volatile DRAM cell which overcomes the limitations of DRAMs and EEPROMs in a compact simplified cell structure that can be fabricated with simplified fabrication techniques.